When testing an integrated circuit (IC), the number of signals driven and received by the test equipment (tester) is typically equal to the number of signal pins of the IC. It is possible for an IC to have hundreds or thousands of signal pins, and the tester that tests these ICs can be very expensive because the cost of a tester is linearly dependent on the number of signals it drives and receives. It is desirable to minimize the number of signals that a tester must drive and receive from an IC, to reduce the cost of the tester or to permit more ICs to be tested in parallel by the tester.
When testing an IC at the wafer level (i.e., while it is still part of a wafer containing many of the ICs), a probe card which allows tester access to the individual ICs typically has the same number of probes as the number of bond pads on the IC. Bond pads are the metal sites to which a wire or solder will eventually be bonded to convey signal and power between an IC and a substrate or pins of an enclosing package. The quality of the probe to bond pad connection, the inductance of the probe card wires and probes, and the capacitances of these wires can all contribute to degraded signal integrity at high frequencies. For these reasons, as well as the material cost of each probe, it is desirable to minimize the number of probes needed for wafer-level testing of each IC.
Typical circuit elements that provide paths for leakage current to and from a circuit node, a pin (or bond pad) of an IC are shown in FIG. 1. The leakage can be caused by many sources, including, but not limited to, electro-static discharge (ESD) protection diodes 19, 20, faulty metal-oxide-semiconductor (MOS) transistor gates 11, 12, pull-up circuits 15, 17, pull-down circuits 16, 18, and other semiconductor elements. Most ICs have specifications stating the maximum leakage current that the IC will have at any input pin or at any 3-state output pin when the output driver is disabled and the pin has high-impedance output. It is therefore important to test that these leakage currents are less than the specified maximum. The purpose of pull-up or pull-down circuits 15-18 is to xe2x80x9cpullxe2x80x9d the voltage of an un-driven pin to a higher or lower voltage such as VDD or VSS. Accordingly, for pins with pull-up or pull-down circuits 15-18, it is usually important to test that the current is between a lower limit and an upper limit.
The standard terms used in industry for denoting input pin DC parameters are: IIL (maximum current for input at logic low), IIH (maximum current for input at logic high), VIL (maximum voltage for input at logic low), and VIH (minimum voltage for input at logic high). The standard terms for denoting output pin DC parameters are: IOL (maximum current for output pin at logic low), IOH (maximum current for output at logic high), VOL (maximum voltage for output at logic low while delivering IOL), and VOH (minimum voltage for output at logic high while delivering IOH).
Leakage current due to intrinsic current through reverse-biased diodes 19, 20 and MOS transistor gates 11, 12 is typically much less than 1 microamp (xcexcA) in a fault-free circuit. Leakage current due to pull-up or pull-down circuitry 15-18 is typically between 10 and 150 xcexcA. In some ICs, for example as shown in U.S. Pat. No. 5,670,890 issued to Colwell et al on Sep. 23, 1997, the pull-up and pull-down circuitry is disabled while testing the leakage current caused by other circuitry.
It is therefore important to be able to set different test limits for different pins. For example, pins with a pull-up circuit may require testing that the current is between xe2x88x9250 and xe2x88x92150 xcexcA; pins with a pull-down circuit may require testing that the current is between +30 and 10 xcexcA; other pins may require the current be between +1 and xe2x88x921 xcexcA.
Throughout this disclosure, the current at a pin is positive if it flows into the IC, and negative if it flows out of the IC, when the pin is connected to any voltage between VDD and VSS. Unsigned current may be positive or negative.
In general, the causes of leakage current are so diverse that the test limits are very tolerant of variation. Nevertheless, measuring currents at hundreds or thousands of pins of an IC can be expensive: the tester must have a parametric measurement unit (PMU) for each pin to allow testing all pins in parallel, or the tester must test one pin at a time if only one PMU is available.
It is typical in industry to specify the maximum leakage current as 1 xcexcA even though the expected current is less than 1 nA, because the test time to verify 1 nA can be excessive. For example, the pin""s capacitance to ground might be 1 picofarad (pF), but the tester coaxial cabling connected to the pin might have capacitance of 50 pF. The time for a 1 nA current to discharge 50 pF by 1 volt, is 50 ms, whereas if 1 xcexcA is used, the discharge time is only 50 xcexcs. Smaller voltage differences can be measured to decrease test time, but noise tolerance diminishes.
A standard technique for testing current at a pin is based upon connecting a current source to the pin, applying a pre-determined current (IIL or IIH, for inputs, and IOL or IOH, for outputs), and measuring the resulting voltage at the pin. This technique is used to measure a very wide range of currents, from amperes to nanoamperes, and can therefore measure output drive current and input leakage current. A standard variation of this technique is to continuously increase the current until a pre-determined pin voltage (VOL or VOH for outputs) is reached. Both techniques require direct connection to the pin under test.
Another prior art technique for testing leakage current at a pin is based upon connecting a voltage source to the pin via a high impedance resistor and measuring the resulting steady-state voltage across the resistor, for example as shown in U.S. Pat. No. 5,569,951 issued to Grace and DiPietro on Oct. 29,1996.
Prior art techniques exist for testing leakage current at a power supply pin of an IC, when all circuitry in the IC is inactive (or xe2x80x9cquiescentxe2x80x9d). This current is known as IDDQ and if it is excessive (e.g., greater than 100 xcexcA), it may indicate that a fault exists somewhere among the thousands of MOS transistors of an IC, because when these transistors are inactive they normally conduct no current between the power and ground supplies. Some prior art IDDQ measuring techniques disconnect the IC from the power supply briefly (e.g., less than 1 ms), when the IC is known to be inactive, and connect the IC to the power supply via a resistance, for example, as shown in U.S. Pat. No. 5,371,457 issued to Lipp on Dec. 6, 1994. By measuring the voltage across the resistance, small currents are measured very quickly, before the voltage at the power supply pin of the IC decreases more than a few hundred millivolts. The power supply voltage is then quickly restored to ensure that no logic state changes are induced on the IC.
One proposed solution for testing ICs with a tester and probe card containing fewer signals and probes than the IC""s number of bond pads, is to use the IEEE 1149.1 (also called JTAG) boundary scan standard for test access. This well-known test standard defines 1149.1-compliant ICs as having a TAP comprising 4 or 5 test pins, a TAP controller, and other on-chip circuitry including a digital shift register to convey logic signals to and from the non-test pins of the IC. One of the test pins, denoted TCK, is a test clock typically having a constant period (e.g., 100 ns). Although not described in 1149.1, if all non-test pins of the IC have both a driver and input logic buffer connected to them, regardless of whether they function as an input, output, or bi-directional pin, then structural integrity of each pin""s driver and input buffer can be tested by performing a xe2x80x9cwrap-aroundxe2x80x9d test.
A wrap-around test consists of driving a pin to each logic value (0, 1), and then sampling the output of the input logic buffer whose input is connected to the pin, after a time interval in which the pin voltage is certain to have settled at a steady-state voltage. This procedure can be performed using test patterns and sequences defined in the 1149.1 standard. The typical test clock frequency ranges from 1 MHz to 20 MHz. Accordingly, for ICs that are compliant with the 1149.1 standard, the shortest time interval between initiating a logic transition at a pin and capturing the resulting value is 2xc2xd clock periods and hence ranges from 2.5 xcexcs to 125 ns. Typical logic transition times at the pins of an IC are between 2 ns and 20 ns.
The procedure described in the preceding paragraph is therefore performed with a sampling clock period that is slow enough to be insensitive to the parametric variations which are described in the next four paragraphs.
The wrap-around test procedure described does not detect excessive leakage current at a pin. For input pins with a pull-up or pull-down circuit, neither insufficient nor excessive pull-up/down current will be detected by the wrap-around test because the pins are always driven with relatively low-impedance drivers. For 3-state output pins, leakage current (while the driver is in high-impedance mode) may indicate a delay fault, an unreliable structure, or some other such subtle defect, none of which would be acceptable or detected by the wrap-around test. The leakage current for a 2-state output driver (with two, low impedance output states) is immaterial because the driver is always driving with low impedance; any leakage could only be detected by an IDDQ test.
The wrap-around test procedure described does not detect insufficient or excessive output drive. The sampling clock period is intentionally chosen to be longer than the time for the slowest pin signal to settle at a steady-state value, so that only catastrophic structural faults are detected.
The wrap-around test procedure described does not detect faults in the input switching point voltage (VSW). Excessive mismatch in the transistor sizes of an input buffer causes its VSW to be too low or too high and degrades noise tolerance for the input, but it does not degrade performance enough to be detected with the relatively noise-free and fast transition times of a simple wrap-around test.
The wrap-around test procedure described does not detect missing bond wire connections between bond pads and package pins because the characteristics of the bond pad are not changed sufficiently by connecting it to a package pin alone (with no connection to the external tester). Testing bond wire integrity is an important test for a packaged IC because the bond wire connection is the only circuitry added to an IC after wafer-level testing.
The problems described for the wrap-around test procedure have discouraged many companies from using the test technique as a way to reduce the number of probes or tester channels connected to an IC under test.
Input current leakage, input switching point voltage tests, and output drive tests are considered by manufacturers and their customers to be important tests. It is therefore desirable to provide a test technique that performs one or more of these tests through a standard test access infrastructure via a small number of probes and tester channels, to enable a higher quality test than is achievable with a conventional wrap-around test while allowing lower cost testing.
The invention described herein uses testing circuitry connected to a circuit node of a circuit under test. The circuit node may be an input or output node, for example an IC bond pad or a IC package pin. The testing circuitry comprises on-chip test circuitry connected to the circuit node. The invention implements a test method that can be performed by applying signals via a test access port to cause a signal transition at the circuit node, and a sampling of the circuit node signal after a predetermined time interval. The test access port may be a TAP controller described in the IEEE 1149.1 standard or one modified. The invention includes circuitry to allow the predetermined time interval to be shorter than possible with the prior art IEEE 1149.1 TAP controller.
In accordance with an aspect of the present invention, there is provided a method for testing current flowing through a circuit node of a circuit under test. The circuit under test includes drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing, and includes a logic circuit that samples the logic level of the circuit node synchronously to a clock signal. The circuit node has a capacitance. The logic circuit has an input switching point voltage. The method comprising the steps of driving the circuit node to a known voltage, via the drive circuitry that drives the circuit node; causing a signal transition at the circuit node, via the drive circuitry; sampling a logic value of a voltage of the circuit node, via the logic circuit, at a predetermined time interval after the beginning of the signal transition, the time interval being less than an expected signal transition time and being proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node; and passing or failing the test, based on the logic value sampled by the logic circuit during the signal transition.
In accordance with another aspect of the invention, there is provided a method for testing current flowing through a circuit node of a circuit under test. The circuit under test includes drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing, and includes a logic circuit that samples the logic level of the circuit node. The circuit node has a capacitance. The logic circuit has an input switching point voltage. The method comprises the steps of providing a first test clock for generating test control signals; providing a second clock with a significantly higher frequency than the first test clock; using an edge of the second test clock, which immediately follows an edge of the first test clock, to generate a signal transition on the circuit node via the drive circuitry; using a subsequent edge of the second test clock to sample the voltage of the circuit node; and controlling a time interval between the edges of the second test clock to be less than an expected transition time of the signal transition and to be proportional to values of the capacitance of the circuit node, the input switching point voltage for the circuit node, and the current flowing through the circuit node.
In accordance with another aspect of the invention, there is provided a control signal modifying circuit for modifying a test control signal generated by a test controller for controlling drive circuitry that drives a circuit node of a circuit under test and logic circuitry that samples the voltage of the circuit node. The test controller has a test clock for generating the test control signal and transitions between states for the test controller. The control signal modifying circuit comprises receiving means, modifying means and outputting means. The receiving means is provided for receiving the test control signal generated by the test controller. The modifying means is provided for modifying the test control signal to provide a predetermined time interval which is less than an expected signal transition time and proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node. The outputting means is provided for outputting the modified test control signal to the drive circuitry and logic circuitry.
In accordance with another aspect of the invention, there is provided testing circuitry for testing current flowing through a circuit node of a circuit under test. The circuit node has a capacitance. The testing circuitry comprises drive circuitry, a logic circuit, a test controller and a control signal modifying circuit. The drive circuitry drives the circuit node to a maximum and to a minimum voltage during testing. The logic circuit samples the logic level of the circuit node synchronously to a clock signal, and has an input switching point voltage. The test controller controls the drive circuitry and the logic circuitry, and has a test clock for generating the test control signal and transitions between states for the test controller. The control signal modifying circuit modifies the test control signal to provide a predetermined time interval which is less than an expected signal transition time and proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node.
Other aspects and features of the present invention will be readily apparent to those skilled in the art from a review of the following detailed description of preferred embodiments in conjunction with the accompanying drawings.